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1995, 1996 data sheet the m pd6464a,6465 are cmos lsis for on-screen character display that control various display systems (such as tape counters) including the program screens of deck-type vcrs and ld players. these lsis are used in combination with a microcomputer. it can display characters each consisting of 12 (horizontal) by 18 (vertical) dots. some chinese characters and some pictograms can also be displayed by combining two or more characters. the m pd6464a,6465 include a power-on clear function and a video ram batch clear command that mitigate the workload of the host microcomputer. it also has a synchronization separator and a 4 multiplier on chip, eliminating the need of connecting an external separator ic and a crystal resonator, which reduces the mounting area and the total cost. features ? video signal input/output : composite video signal ? number of display characters : 12 lines, 24 columns (288 characters) ? number of character types : 128 ( m pd6464a)/256 ( m pd6465) (rom). variable by mask code option. ? character size : 1 dot/1 line. 2 lines (field) can be displayed in line units. ? character color : white (single color) ? background : no background, black framing, black-on-white, and black filling ? dot matrix : 12 (horizontal) 18 (vertical) dots without gap between adjacent characters ? blinking : blinking can be turned on/off in character units. blinking ratio is 1:1. blinking frequency is selectable from about 0.5 hz, 1 hz, and 2 hz in screen units. ? character signal output: : can support vcrs with s pins if external mixer is connected because character signal and blanking signal output pins are provided. ? video ram data clear : video ram data are cleared by video ram clear command and power-on clear function. ? supported video signal method : ntsc/pal/pal-m/secam/pal-n ( m pd6464a only) ? internal circuit : synchronization separation circuit for composite synchronizing signal and 4 multiplier ? interface with microcomputer : serial input type of 8-bit variable word length ? supply voltage : +5 v, single power supply ordering information part number package m pd6464acs- 24-pin plastic shrink dip (300 mil) m pd6465cs- 24-pin plastic shrink dip (300 mil) m pd6464agt- 24-pin plastic sop (375 mil) m pd6465gt- 24-pin plastic sop (375 mil) remark : rom code suffix (cs-001, gt-101 : nec standard device) the information in this document is subject to change without notice. document no. s11043ej4v0ds00 (4th edition) date published may 1998 n cp(k) printed in japan mos integrated circuit m pd6464a,6465 on-screen character display cmos lsi for 12-line, 24-column deck-type vcr the mark shows major revised points.
m pd6464a,6465 2 block diagram note m pd6464a only 3 1 2 6 5 17 15 13 14 23 24 4 8 19 7 v dd gnd test pcl vbsi v cnt v blk v c xosi xoso hsyo csyin osc out osc in data clk cs data input shift register data buffer register instruction decoder control signal external/ internal register ntsc/ pal/ pal-m/ secam/ pal-n note register character size register horizontal address register write address counter data selector video ram background control data register display control data register horizontal size counter horizontal position counter horizontal address counter character data 7 bits ( pd6464a) 8 bits ( pd6465 ) 288 words blink data 1 bit 288 words vertical address register oscillation circuit timing generator vertical size counter vertical position counter vertical address counter synchronization signal separa- tion circuit mode selection synchronization signal generator 4 multiplier/ 4f sc crystal oscillation circuit output controller character generator rom 12 18 bits 128 words ( pd6464a) 256 words ( pd6465) osc l oscin c oscout c 16 vsyo 10 9 11 12 fsci fsco 20 nre 21 vbso 22 secam m m m m
m pd6464a,6465 3 pcl : power-on clear secam : secam subcarrier input test : test pin v blk : blanking signal output vbsi : composite video signal input vbso : composite video signal output v c : character signal output v cnt : video signal output level adjustment v dd : power supply vsyo : vertical synchronization signal output xoso : quadruple oscillation output xosi : quadruple oscillation input clk : clock input cs : chip select input csyin : composite synchronization signal input data : serial data input fsci : f sc signal input fsco : frequency error output gnd : ground hsyo : horizontal synchronization signal output n.c. : no connection nre : noise reduction constant append osc in : lc oscillation input osc out : lc oscillation output pin configuration (top view) 24-pin plastic shrink dip (300 mil) m pd6464acs- m pd6465cs- 24-pin plastic sop (375 mil) m pd6464agt- m pd6465gt- 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk cs data v dd osc out osc in pcl gnd fsci fsco xoso xosi vbsi v cnt secam vbso nre test n.c. csyin vsyo hsyo v blk v c remark : rom code suffix (cs-001, gt-101: nec standard device)
m pd6464a,6465 4 pin functions no. symbol pin name 1 clk clock input 2 cs chip select input 3 data serial data input 4v dd power supply 5 osc out lc oscillation output 6 osc in lc oscillation input 7 pcl power-on clear 8 gnd ground 9 fsci f sc signal input 10 fsco frequency error output 11 xoso quadruple oscillation output 12 xosi quadruple oscillation input 13 v c character signal output 14 v blk blanking signal output 15 hsyo horizontal synchronization signal output 16 vsyo vertical synchronization signal output 17 csyin composite synchronization signal input 18 n. c. non connection 19 test test pin 20 nre noise reduction constant append 21 vbso composite video signal output 22 secam secam subcarrier input 23 v cnt video signal output level adjust- ment 24 vbsi composite video signal input function inputs clock for data read. data input to the data pin is read at the rising edge of the clock input to this pin. serial transfer can be acknowledged by making this cs pin low. inputs control data. data is read in synchronization with the clock input to the clk pin. supplies power to the ic. these are input and output pins of an oscillator that generates dot clocks. connect a coil and a capacitor to these pins for oscillation. power-on clear pin. make this pin high on power application. it initializes the internal circuitry of the ic. ground pin of the ic. in case of the 4 multiplier, the color sub-carrier (f sc ) is input to this pin. in case of the 4f sc crystal oscillation, connect this pin to gnd or v dd . the frequency error signal of the 4 multiplier is output to this pin. in case of the 4f sc crystal oscillation, this pin should be open. a quadruple oscillation lc for internal video signal generation is connected to these pins. a crystal oscillator can also be connected. character signal output pin. positive signal output. this pin outputs a blanking signal that cuts the video signal. it corresponds to the output of v c . positive signal output. outputs a horizontal synchronization signal separated from a composite synchronization signal. outputs a vertical synchronization signal separated from a composite synchronization signal. a composite synchronization signal is input to this pin for synchronization signal separation. in case of the external signal mode, input the signal certainly. input a positive synchronization signal. non connection. leave this pin open. test mode select pin. connect this pin to gnd. constant append pin for noise reduction. outputs a composite video signal mixing a character signal. secam sub-carrier signal mixing pin. in cases of any system except for secam, this pin should be open. adjusts the output level of the composite video signal and luminance signal. inputs a composite video signal. inputs a signal with the leading edge clamped, consisting of a negative synchronization signal and a positive video signal.
m pd6464a,6465 5 contents 1. commands ..................................................................................................................... ............... 7 1.1 command format .............................................................................................................. ... 7 1.2 command list ................................................................................................................ ....... 7 1.3 power-on clear function .................................................................................................... 8 2. command details ............................................................................................................. ........ 8 2.1 video ram batch clear command ..................................................................................... 8 2.2 display control command ................................................................................................... 9 2.3 internal video signal color control command .................................................................. 10 2.4 background control command ........................................................................................... 10 2.5 internal/external mode control, crystal oscillation control command .......................... 14 2.6 video signal method control command ............................................................................ 15 2.7 oscillation method control command ............................................................................... 16 2.8 display position control command .................................................................................... 17 2.9 write address control command ....................................................................................... 19 2.10 output level control command .......................................................................................... 20 2.11 character size control command ....................................................................................... 21 2.12 test mode command .......................................................................................................... .. 22 2.13 display character control command (2-byte contiguous command) ............................ 22 3. transferring commands ..................................................................................................... 23 3.1 1-byte command .............................................................................................................. .... 23 3.2 2-byte command .............................................................................................................. .... 23 3.3 2-byte contiguous command ............................................................................................. 23 3.4 successive command input ................................................................................................ 24 3.4.1 when 2-byte contiguous command end code is not used ..................................... 24 3.4.2 when 2-byte contiguous command end code is used ............................................ 24 3.5 busy period for command input ........................................................................................ 25 3.5.1 when inputting 1-byte or 2-byte command .............................................................. 25 3.5.2 when inputting 2-byte contiguous command .......................................................... 25 4. adjusting .................................................................................................................... ................. 27 4.1 adjusting oscillation frequency ......................................................................................... 27 4.1.1 adjusting 4 multiplier and crystal oscillation frequency ...................................... 27 4.1.2 adjusting lc oscillation frequency (dot clock) ....................................................... 27 4.2 test mode clear command .................................................................................................. 28 4.3 clamp level of video signal ................................................................................................ 2 8 5. composite sync. signal separation circuit ................................................................. 30 6. character pattern data .................................................................................................... 3 2 6.1 standard character patterns of the m pd6464a .................................................................. 33 6.2 standard character patterns of the m pd6465 .................................................................... 36
m pd6464a,6465 6 7. electrical specifications ................................................................................................... 42 8. application circuit diagram ............................................................................................. 46 9. package drawings ........................................................................................................... ...... 48 10. recommended soldering conditions ............................................................................. 50
m pd6464a,6465 7 1. commands 1.1 command format control commands are of variable length in 8-bit units and are input in serial. three types of commands are available: 1-byte commands consisting of 8 bits of instruction and data in combination, 2-byte commands of 16 bits of instruction and data in combination, and a 2-byte contiguous command that can be abbreviated for input. input command data from the msb first. 1.2 command list 1-byte commands function d7 d6 d5 d4 d3 d2 d1 d0 video ram batch clear 00000000 display control 0001d0lcbl1bl0 internal video signal color control 0010rgb0 background control 00110bs1 bs00 internal/external mode control, crystal 01000e/i0x osc oscillation control video signal method control 01001 n/p2 n/p1 n/p0 oscillation method control 010100xf c 0 2-byte commands function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 display position control 100000v4v3v2v1v0h4h3h2h1h0 write address control 1000100ar3ar2ar1ar0ac4ac3ac2ac1ac0 output level control 1001000vpd000001vc1vc0 character size control 100110000s000ar3ar2ar1ar0 test mode note 10110000t7t6t5t4t3t2t1t0 note must not be used. 2-byte contiguous command function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 display character 110000bl0 c7 c6 c5 c4 c3 c2 c1 c0 control note fixed to "0" ( m pd6464a) (msb) (msb) (msb) note
m pd6464a,6465 8 1.3 power-on clear function because the internal status of the ic is unstable on power application, initialize the ic by making the pcl pin high and executing a clear operation. when the clear operation has been performed, the following setting is made: ? test mode is cleared. ? all the character data of the video ram (12 lines, 24 columns) are set to display off data (7e h ( m pd6464a)/fe h ( m pd6465)) and the blinking data are set to off. ? video ram write address (line 0, column 0) is set. ? character size is set to 1 (minimum) on all lines. ? display is turned off and lc oscillation is turned on. the time required for the power-on clear operation can be calculated by the following expression: t = t pcll note + {video ram clear time} = 10 ( m s) + {10 ( m s) + 12/f osc (mhz) 288 [ m s]} note refer to 7. electrical specifications power-on clear specification . remark f osc : lc oscillation frequency (dot clock frequency) 2. command details 2.1 video ram batch clear command this command can clear the video ram with a single command. d7 d6 d5 d4 d3 d2 d1 d0 00000000 the video ram batch clear command performs the following setting: ? sets all the character data of the video ram (12 lines, 24 columns) to display off data (7e h ( m pd6464a)/fe h ( m pd6465)) and blinking data to off. ? sets a video ram write address (line 0, column 0). ? sets the character size to 1 (minimum) on all lines. ? turns display off and lc oscillation on. the time required for clearing the video ram can be calculated by the following expression: t = video ram clear time = 10 ( m s) + 12/f osc (mhz) 288 [ m s] remark f osc : lc oscillation frequency (dot clock frequency)
m pd6464a,6465 9 2.2 display control command this command turns on/off the display and controls lc oscillation and blinking of characters. d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 d0 lc bl1 bl0 blinking control bits bl1 bl0 00 01 11 function blinking off blinking frequency: about 2 hz blinking frequency: about 0.5 hz display on/off control bit d0 0 1 function display off display on lc oscillation control bit lc 0 1 function lc oscillation off lc oscillation on 10 blinking frequency: about 1 hz ? blinking control bits these bits blink the character that is specified by the display character control command. the blinking ratio is 1:1, and three blinking frequencies can be selected. blinking in character units can be specified by the display character control command. ? lc oscillation control bit this bit controls lc oscillation and can turn on/off the oscillation circuit. while no character is displayed, oscillation can be stopped to reduce the power dissipation. data cannot be written to the video ram with oscillation stopped. to write data to the video ram, be sure to turn on oscillation. remark oscillation is synchronized with hsync when display is on and lc oscillation is on, and oscillation is stopped while hsync is low. when display is off and lc oscillation is on, oscillation is performed, regardless of the level of hsync. ? display on/off control bit this bit turns on/off the display output. the display is turned on/off in synchronization with the fall of hsync.
m pd6464a,6465 10 2.3 internal video signal color control command this command sets the color of an internal video signal. the internal video signal is a video signal (e.g., blue back) internally generated by the m pd6464a, 6465. while no external video signal is input to the m pd6464a, 6465 and therefore no character can be displayed, if the internal video signal is selected, characters can be displayed. d7 d6 d5 d4 d3 d2 d1 d0 0010rgb0 internal video signal color control bits rg 00 00 01 function black blue setting prohibited 01 green b 0 1 1 0 10 10 11 11 0 1 1 0 setting prohibited setting prohibited white setting prohibited ? internal video signal color control bits these bits can select four colors as the color of the internal video signal. 2.4 background control command this command selects the background of the displayed character. d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 1 0 bs1 bs0 0 background control bits bs1 bs0 00 01 11 function no background black framing black filling 10 black-on-white
m pd6464a,6465 11 ? background control bits these bits select the type of background in screen units from none, black-framed, black-on-white, or black-filled background. no background : only character data are output. black framing : if the left- and rightmost columns or the top and bottom lines of a dot matrix are not used, the displayed character can be framed horizontally, vertically, or diagonally. when the dots on the rightmost or leftmost column of the dot matrix are used, a frame is displayed in the adjacent character display areas. even when the dots on the top and bottom lines of the dot matrix are used, the lines above and below the dot matrix are not framed. even if the character size is changed, the size of black framing is fixed to 1 dot, which is the minimum size. black-on-white : a black background is displayed on the rightmost and leftmost positions of the display area of the character written to the video ram with 1 extra dot, which is the minimum size, at both positions. black filling : a black background is displayed outside the character display area, in addition to the black- on-white background.,
m pd6464a,6465 12 display format in each background mode filling note data display off data display off data display off data display off data 12 dots 1 dot 1 dot 1 dot 1 dot 1 dot 1 dot 10 dots 18 dots 10 dots character (white) image character (white) framing (black) image character (white) background (black) image character (white) background (black) image 12 dots filling note data 12 dots 12 dots 18 dots filling note data filling note data black framing no backgraund black filling black-on-white note filling data means 1f h ( m pd6464a), 6e h ( m pd6465) with the necs standard character.
m pd6464a,6465 13 example of display when display off data is used ? black-on-white background 0 1 20 21 22 23 12 dots 18 dots display off data display off data display off data display off data background output for 1 dot background output for 1 dot external or internal video signal background output for 1 dot column 12 dots 12 dots 12 dots the background color is output on 1 dot on both the edges of display off data when the display off data is used. ? black-filled background 0 1 20 21 22 23 18 dots display off data display off data display off data display off data background background background output for 1 dot background output for 1 dot background output for 1 dot external or internal video signal column 12 dots 12 dots 12 dots 12 dots the background color is output on 1 dot on both the edges of display off data when the display off data is used. remark the background output for 1 dot does not change by 1 dot, which is the minimum size, even when the character size is changed.
m pd6464a,6465 14 2.5 internal/external mode control, crystal oscillation control command this command selects the video signal with which a character signal overlaps (internal mode/external mode) and controls on/off of crystal oscillation. d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 0 e/i 0 x osc crystal oscillation control bit x osc 0 1 function oscillation off oscillation on internal/external mode control bit e/i 0 1 function external video signal mode internal video signal mode ? crystal oscillation control bit this bit controls oscillation of the crystal for internal video signal generation. when crystal oscillation is turned on and the mode is changed from the external video signal mode to the internal video signal mode, the internal video signal is selected without the screen disturbed. when crystal oscillation is turned off, the synchronization separation circuit does not operate. be sure to turn on crystal oscillation. ? internal/external mode control bit external video signal mode : in this mode, character signals are output to the m pd6464a and 6465, overlapping the external video signal that is input from external. the overlapped signal is output to the vbso pin. if character signals should not be overlapped, set the display on/off control bit to 0 (display off) with the display control command. moreover, a composite synchronization signal (csync), which synchronizes with the video signal input from external, is required to be input from the csyin pin. if no csync exists, input the composite synchronization signal generated from the input video signal via the composite sync signal separation circuit (refer to 5. composite sync. signal separation circuit ). in the timing generator block built in the m pd6464a and 6465, a horizontal synchronization signal and a vertical synchronization signal are generated by separating from a composite synchronization signal synchronously. a reference signal is generated from these synchronous signals. the reference signal is used to reset and count the horizontal control block, vertical control block, and output control block. if csync is not input, characters may not be displayed because the reference signal is not generated in the timing generator block. internal video signal mode : in this mode, characters are output overlapping the video signal that is created in the m pd6464a and 6465 (e.g., blue back signal) to the vbso pin. in the internal video signal mode, characters can be displayed on the screen because horizontal and vertical synchronization signals are generated in a device, even if no composite synchronization signal is input.
m pd6464a,6465 15 2.6 video signal method control command the m pd6464a, 6465 can select the ntsc, pal, and pal-m methods for the internal video signal. the m pd6464a can also select the pal-n method. when the secam method is selected, the internal video signal is output by the pal method. d7 d6 d5 d4 d3 d2 d1 d0 01001 n/p2 note n/p1 n/p0 video signal method control bits n/p1 n/p0 00 01 11 function ntsc pal secam 10 pal-m n/p2 0 0 0 0 00 pal-n 1 setting prohibited note fixed to 0 ( pd6465). m ? video signal method control bits these bits can generate internal ntsc, pal, pal-m and pal-n ( m pd6464a only) video signals. with the secam method, however, a color subcarrier from the secam color subcarrier input pin (pin 22) is fixed in the external mode. in the internal mode, an internal pal video signal is generated. the internal video signal is generated by using a 4 multiplier or an external crystal. use a crystal with a frequency of 4 f sc for each video signal.
m pd6464a,6465 16 2.7 oscillation method control command the m pd6464a, 6465 can select a crystal for internal video signal generation or a 4 multiplier. d7 d6 d5 d4 d3 d2 d1 d0 01010 0xf c 0 oscillation method control bit xf c 0 1 function quadruple oscillation 4f sc crystal oscillation ? oscillation method control bit in the m pd6464a and 6465, the oscillation method can be selected from 4 multiplication oscillation and 4f sc crystal oscillation with the oscillation method control command. when 4 multiplication oscillation is selected, the f sc signal must be input from the fsci pin. the 4f sc signal is generated from an external lc resonator and an internal circuit of the m pd6464a and 6465. the phase of four- divided 4f sc signal generated via lc oscillation is compared with that of the f sc signal that is input to the fsci pin. the obtained phase error is converted to a voltage value, and then output from the fsco pin. in the circuit shown in 8. application circuit diagram (1) in 4 multiplication oscillation , the 4f sc signal synchronizing with the external f sc signal is generated by changing the capacitance of varactor diodes with this voltage that is based on a phase error. when 4f sc crystal oscillation is selected, the fsci and fsco pins are not used. these pins should be connected as follows. fsci pin (pin 9) : connect to gnd or v dd . fsco pin (pin 10) : leave open. remark the scanning method in the internal video signal mode is non-interlacing. with the ntsc and pal- m methods, the number of scanning lines is 263. with the pal and pal-n method, it is 312.
m pd6464a,6465 17 2.8 display position control command this command can set the display start position in 12-dot units and 32 steps in the horizontal direction, and in 9-line units and 32 steps in the vertical direction. because this command is a 2-byte command, it must be input in 16-bit units even when the command is successively input. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 0 v4 v3 v2 v1 v0 h4 h3 h2 h1 h0 horizontal display start position control bit h4 h3 h2 h1 000 0 000 0 111 1 function from rising of hsync (12 1)/f osc +4/f osc ( s) from rising of hsync (12 2)/f osc +4/f osc ( s) from rising of hsync (12 32)/f osc +4/f osc ( s) h0 0 1 1 m m m vertical display start position control bit v4 v3 v2 v1 000 0 000 0 111 1 function from rising of vsync 9h 0 from rising of vsync 9h 1 from rising of vsync 9h 31 v0 0 1 1 remark f osc : lc oscillation frequency (dot clock frequency) remark h: line
m pd6464a,6465 18 ? horizontal display start position control bits the horizontal display start position can be set in 12-dot units and 32 steps, 16 clocks after the rising of the horizontal synchronization signal (hsync) (16/f osc (mhz)). ? vertical display start position control bits the vertical display start position can be set in 9-line units and 32 steps, from the rising of the vertical synchronization signal (vsync). a b display area (12 lines 24 columns) horizontal synchronization signal (hsync) vertical synchronization signal (vsync) a: 9h (line) (2 4 v 4 + 2 3 v 3 + 2 2 v 2 + 2 1 v 1 + 2 0 v 0 ) 12 16 b: (2 4 h 4 + 2 3 h 3 + 2 2 h 2 + 2 1 h 1 + 2 0 h 0 ) + f osc (mhz) f osc (mhz) remark f osc : lc oscillation frequency (dot clock frequency) hsync and vsync, which serve as references, are as follows: internal video signal mode : hsync and vsync are generated by internal circuit. external video signal mode : hsync and vsync are generated from composite synchronization signal, input to csyn pin (pin 17), by sync. signal separation circuit.
m pd6464a,6465 19 2.9 write address control command this command specifies a write address when a character is written to the display area (video ram) of 12 lines by 24 columns. because this command is a 2-byte command, it must be input in 16-bit units even when input successively. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 1 0 0 ar3 ar2 ar1 ar0 ac4 ac3 ac2 ac1 ac0 write column address control bits ac4 ac3 ac2 ac1 000 0 000 0 function sets column 0 sets column 1 setting prohibited ac0 0 1 101 1 sets column 23 1 write line address control bits ar3 ar2 ar1 00 0 00 0 function sets line 0 sets line 1 setting prohibited ar0 0 1 10 1 sets line 11 1 ? write column address control bits one line consists of 24 columns in the horizontal direction. these bits specify the column to be written. ? write line address control bits one column consists of 12 lines in the vertical direction. these bits specify the line to be written. video ram configuration the video ram consists of 12 lines by 24 columns as shown below. the number of display characters therefore is 12 lines by 24 columns (when all the lines are set to the minimum size). ac4, ac3, ac2, ac1, ac0 00000 00001 00010 10110 10111 ar3, ar2, ar1, ar0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
m pd6464a,6465 20 2.10 output level control command the m pd6464a, 6465 can set the luminance level of the character and background (including the frame) by using a command. this command is a 2-byte command, and must be input in 16-bit units even when successively input. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 100100 0vpd00 0001vc1vc0 character level control bits vc1 vc0 0 1 1 1 function 75 i.r.e. 90 i.r.e. setting prohibited internal video signal amplitude control bit vpd 0 1 function 1 v p-p amplitude 2 v p-p amplitude 1 0 setting prohibited 0 0 ? character level control bits these bits can select two character luminance levels: 75 or 90 i.r.e. if these bits are not set, the character level is set to 75 i.r.e. remark the background (frame) level is fixed to 0 i.r.e. ? internal video signal amplitude control bit this bit sets the amplitude of the internal video signal to 1 or 2 v p-p (this amplitude must match the amplitude of the signal input in the external video signal mode). when the amplitude is set to 1 v p-p , the voltage applied to the v cnt pin must be 2.5 v. when the amplitude is set to 2 v p-p , apply 5 v to the v cnt pin.
m pd6464a,6465 21 2.11 character size control command this command can set the character size in line units (in both the horizontal and vertical directions). because this is a 2-byte command, it must be input in 16-bit units even when successively input. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1001100 00s000ar3ar2ar1ar0 line specification control bits ar3 ar2 ar1 ar0 000 0 000 1 101 1 function sets line 0 sets line 1 sets line 11 setting prohibited character size control bit s0 0 1 function vertical 1 dot: 1h, horizontal 1 dot: 1t dot (minimum size) vertical 1 dot: 2h, horizontal 1 dot: 2t dots ? line specification control bits these bits specify the character size in line units, and control which line is to be specified. ? character size control bit this bit selects the character size in two steps. display with two character size specified example of display screen line 0: minimum size (vertical 18h/horizontal 12 dots) line 1: 2 times (vertical 36h/horizontal 24 dots) line 2: minimum size external video signal, etc. line 3: 2 times line 4: minimum size line 5: 2 times line 6: 2 times line 7: minimum size lines 8 to 11 are omitted because they overflow from the screen. the size in the vertical direction (the number of horizontal scanning lines) is the size in field units. 1t dot = m s f osc : lc oscillation frequency 1 f osc (mhz)
m pd6464a,6465 22 2.12 test mode command this command is for testing the ic. do not set this command. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 10110000t7t6t5t4t3t2t1t0 [reference] test mode clear command d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1011000000000000 2.13 display character control command (2-byte contiguous command) this command specifies the character data and blinking data to be written to the video ram. when inputting this command, turn on lc oscillation (if lc oscillation is turned off, no character can be written to the video ram). because this command is a 2-byte contiguous command, if character data are successively written without the blinking data changed, the second character and those that follow can be abbreviated to the lower 8 bits (d7 to d0). in this case, the write column address is automatically incremented (if a character is written to column 23 at the rightmost position, the next write address is automatically incremented to column 0 of the next line (leftmost position)). notes 1. fixed to "0" ( m pd6464a). 2. 7e h ( m pd6464a), fe h ( m pd6465). 3. 7f h ( m pd6464a), ff h ( m pd6465). d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1100 00bl0c7c6c5c4c3c2c1c0 character specification bits c6 c4 c3 c1 000 0 000 0 111 1 function outputs data of 00 h outputs data of 01 h outputs data display off c0 0 1 0 c2 0 0 1 c5 0 0 1 111 1 end code of 2-byte contiguous command 1 1 1 blink control bit bl 0 1 function does not blink character blinks character column address 0 1 2 22 23 0 1 2 10 11 line address line address incremented note 2 c7 0 0 1 1 note 3 note 1
m pd6464a,6465 23 ? character specification bits these bits specify the address of a character. there are 128 types of characters available ( m pd6465: 256 types). addresses 7e h ( m pd6464a), fe h ( m pd6465), 7f h ( m pd6464a) and ffh ( m pd6465), however, are fixed to the display off data and 2-byte contiguous command end code, respectively (no character can be set to these addresses even when the character is changed by mask code option because these addresses are fixed nevertheless). the character designs can be changed by mask code option. ? blink control bit this bit specifies whether the character written to the video ram blinks, in character units. for the details of turning on/off blinking in screen units, refer to 2.2 display control command . 3. transferring commands 3.1 1-byte command data clk cs 3.2 2-byte command data clk cs 1st byte 2nd byte 1st byte: d15-d8 2nd byte: d7-d0 when transferring a 2-byte command, keep cs low between the first byte and second byte. 3.3 2-byte contiguous command data clk cs 1st byte 2nd byte 2nd byte the 2-byte contiguous command writes a character to the video ram. to write characters in succession without changing the blink data, first transfer the first byte and then transfer the second bytes (character addresses) in succession.
m pd6464a,6465 24 3.4 successive command input transfer each of the 1-byte, 2-byte, and 2-byte contiguous commands from a microcomputer to the m pd6464a, 6465 as described below. when transferring a 1-byte command, 2-byte command, or a 2-byte contiguous command with the blink data changed after a 2-byte contiguous command has been transferred, either make cs high once, or transfer end code of the 2-byte contiguous command note at the end of the 2-byte contiguous command. in the latter case, cs needs not to be made high. note 7f h ( m pd6464a), ff h ( m pd6465) 3.4.1 when 2-byte contiguous command end code is not used example 1-byte command ? 2-byte contiguous command ? 1-byte command cs must be made high once. 1-byte command 1st byte 1-byte command 2nd byte normal character note 2nd byte normal character note d7 - d0 d15 - d8 d7 - d0 d7 - d0 d7 - d0 data clk cs 2-byte contiguous command note 00 h -7e h ( m pd6464a), 00 h -fe h ( m pd6465) 3.4.2 when 2-byte contiguous command end code is used example 1-byte command ? 2-byte contiguous command ? 1-byte command cs needs not to be made high. 1-byte command 1st byte 1-byte command 2nd byte normal character note 1 2nd byte 2-byte contiguous command end code note 2 d7 - d0 d15 - d8 d7 - d0 d7 - d0 d7 - d0 data clk cs 2-byte contiguous command notes 1. 00 h -7e h ( m pd6464a), 00 h -fe h ( m pd6465) 2. 7f h ( m pd6464a), ff h ( m pd6465) remark although the cs pin can remain low when the end code of the 2-byte contiguous command is used, making this pin high is recommended as a countermeasures against noise.
m pd6464a,6465 25 3.5 busy period for command input the busy period for command input is distinguished depending on whether a 1-byte, 2-byte, or 2-byte contiguous command is used. when inputting 2-byte contiguous command, there are two timings as shown below, (1) not transferring 2- byte contiguous command in vsync period with detecting vsync and (2) transferring 2-byte contiguous command in vsync period without detecting vsync. when inputting commands in succession, observe the following timing: 3.5.1 when inputting 1-byte or 2-byte command tb1 clk parameter symbol condition min. typ. max. unit command continuous tb1 1-byte or 2-byte command 2.0 m s input enable time 1 3.5.2 when inputting 2-byte contiguous command (1) not transferring 2-byte contiguous command in vsync period with detecting vsync (command continuous input enable time 2 = tb2) clk tb1' tb2 parameter symbol condition min. typ. max. unit command continuous tb2 2-byte contiguous command display on tb1 + (21/f osc ) s 1 + t hwl1 m s input enable time 2 (= video ram write command) display off tb1 + (21/f osc ) s 1 remark f osc : clock frequency of lc oscillation s 1 : character size t hwl1 : hsync width tb1 3 2.0 m s
m pd6464a,6465 26 (2) transferring 2-byte contiguous command in vsync period without detecting vsync (command continuous input enable time 2 = tb2) clk tb2' parameter symbol condition min. typ. max. unit command continuous tb2 2-byte contiguous command (= video ram (21/f osc ) s 2 + t hwl2 m s input enable time 2 write command), display on remark f osc : clock frequency of lc oscillation s 2 : character size of the first line t hwl2 : hsync period
m pd6464a,6465 27 4. adjusting this section describes how to adjust each circuit of the m pd6464a, 6465. when performing adjustment, the test pin (pin 19) must be connected to v cc . 4.1 adjusting oscillation frequency 4.1.1 adjusting 4 multiplier and crystal oscillation frequency the m pd6464a, 6465 generate the internal video signal by means of quadruple oscillation of 4f sc or crystal oscillation. the oscillation frequency of 4f sc can be output from the vsyo pin (pin 16) by using the test mode command. adjustment ? connect the test pin (pin 19) to v cc (normally, connect this pin to gnd). ? input the following command. the quadrupled or crystal oscillation frequency will be output from the vsyo pin (pin 16). to clear the test mode, either transfer the test mode clear command, or connect the test pin to gnd. ? in this case, the vsyo pin does not function as a vertical synchronization signal output pin. ? adjust the frequency with a capacitor (or coil), connected to xosi pin (pin 12), shown in 8. application circuit diagram using a frequency counter. crystal oscillation frequency output command (2-byte command) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1011000000111111 4.1.2 adjusting lc oscillation frequency (dot clock) the m pd6464a, 6465 create the dot clock of characters by means of lc oscillation. the lc oscillation frequency can be output from the hsyo pin by using the test mode command, in the same manner as when adjusting the crystal oscillation frequency described in 4.1.1. adjustment ? connect the test pin (pin 19) to v cc (normally, connect this pin to gnd). ? input the following command. the lc oscillation frequency will be output from hsyo pin (pin 15). to adjust the lc oscillation frequency, turn off display. when display is on and while hsync is low, oscillation is stopped and the accurate oscillation frequency cannot be obtained (when using a frequency counter). to clear the test mode, either transfer the test mode clear command, or connect the test pin to gnd. ? in this case, the hsyo pin does not function as a horizontal synchronization signal output pin. ? adjust the frequency with a trimmer capacitor (or coil), connected to osc in pin (pin 6) shown in 8. application circuit diagram using a frequency counter. lc oscillation frequency output command (2-byte command) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1011000000111111
m pd6464a,6465 28 4.2 test mode clear command the command that clears the test mode is as follows: d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1011000000000000 caution be sure to connect the test pin to v cc when performing the above adjustment. be sure to connect the test pin to gnd after adjustment. 4.3 clamp level of video signal match the clamp level of the composite video signal input to the m pd6464a, 6465 with the internal video signal level of the m pd6464a, 6465. otherwise, the character level in the external video signal mode will differ from that in the internal video signal mode. adjustment the internal video signal level of the m pd6464a, 6465 is set by the voltage applied to the v cnt pin and an output level control command. the amplitude level of the internal video signal, sync-chip level, and pedestal level can be set in the following combination: specified by output internal video signal sync-chip level pedestal level v cnt pin voltage level control amplitude level (v dd = 5.0 typ.) (v dd = 5.0 typ.) command (v dd = 5.0 typ.) (v syt ) (v ped ) 2.5 v selects 1 v p-p 1 v p-p 1 v 1.29 v 5.0 v selects 2 v p-p 2 v p-p 1 v 1.58 v adjust the sync-chip and pedestal levels of the external video signal to the same level of the internal video signal by using a variable resistor (pin 23) shown in 8. application circuit diagram . when setting the video amplitude level to 1 v p-p , connecting a variable resistor to the v cnt pin is recommended to adjust the internal video signal level (when setting the video signal to 2 v p-p , connect the v cnt pin to the power supply (5 v)).
m pd6464a,6465 29 v syt and v ped levels of composite video signal v ped v syt gnd match the level output from the vbsi pin in the external video signal mode with the level output from the same pin in the internal video signal mode. input level in external video signal mode (when video signal of 1 v p-p is input) 5 v rv cnt v cnt vbsi vbso voltage applied to v cnt pin by rv cnt = 2.5 v v syt = 1.0 v clamp input to input an external video signal with an amplitude of 2 v p-p , input a 1.0-v clamp signal to v syt , apply 5.0 v to the v cnt pin, and set the amplitude of 2 v p-p by using the output level control command.
m pd6464a,6465 30 5. composite sync. signal separation circuit an example of composite sync. signal separation circuit is shown in figure 5-1. figure 5-1. composite sync. signal separation circuit (a) example of composite sync. signal separation circuit r1 = 5.1 k w , r2 = 1.2 k w , r3 = 1 k w , r4 = 220 w , r5 = 100 k w , r6 = 10 k w , r7 = 1 k w , r8 = 2.2 k w , r9 = 10 k w , c1 = 10 m f, c2 = 1 m f, c3 = 1000 pf (b) image of sync. signal separation waveform the slice level (v s ) of figure 5-1 (a) is defined as follows. v s = 2.7 r5 t 2 = 74 mv r4 t 1 . . r1 r3 r5 r2 q1 a b + + c1 c2 composite video signal (2 v p-p ) v c c i sp i x r4 r8 r9 c3 q2 r6 r7 q3 v dd = 5 v composite sync. signal (sync. positive) 0.7 v dd (min.) 0.3 v dd (max.) input to pin 17 t 1 t 2 t 1 = 4.7 s t 2 = 58.86 s v c2 d v c v c3 v c1 m m
m pd6464a,6465 31 when v s is small, it is suited for horizontal sync. separation, but is against to vertical sync. separation. and when v s is large, edge noise of horizontal sync. separation causes a synchronization error (jitter). therefore, the constant of each element in the circuit should be optimized according to input signals characteristics. the c2 capacitance should be specified as a sufficient larger value compared to charge/discharge current. if the value overly exceeds the suitable value, however, excessive response characteristics will be inferior, falling to trace rapid average-picture-level (apl) fluctuation of input signal. in the circuit shown in figure 5-1 (a), a capacitor is connected to the composite video signal input portion for measurement. however, this makes it hard to trace apl fluctuation. therefore, in designing an actual circuit, insert a sync-chip clamp in front of q1 in figure 5-1 (a). to stabilizes the potential of a synchronization signal, for tracing apl fluctuation. caution in the circuit of figure 5-1 (a), the width of the hsync synchronization signal that is included in the composite synchronization signal after separation may be wider than that of the hsync synchronization signal that is included in the input video signal, because of its circuit configuration. therefore, the width of the hsync synchronization signal during a command continuous input enable time (refer to 3.5 busy period for command input) should be the same as that of the hsync synchronization signal included in csync after separation in the circuit of figure 5-1 (a).
m pd6464a,6465 32 6. character pattern data the only difference between the m pd6464acs-001 and m pd6464agt-101 is the package. the character patterns in the character roms of both the models are the same. the same applies to the m pd6465cs-001 and the m pd6465gt-101. both the m pd6464acs-001 and m pd6464agt-101 can display 128 types of alphanumeric characters and character patterns such as kanji, hiragana, and katakana. the m pd6465cs-001 and m pd6465gt-101 can display 256 types of them. the contents of the character rom (character design) can be changed by mask code option. however, the characters at addresses 7e h and 7f h ( m pd6464a)/fe h and ff h ( m pd6465) are fixed to [display off data] and [2-byte contiguous command end code], respectively, and no character patterns can be set to these addresses. although 10 h ( m pd6464a)/6f h ( m pd6465) (blank data) and 7e h ( m pd6464a)/fe h ( m pd6465) (display off data) of the necs standard model are represented in the same manner in the page showing the character patterns (i.e., these are shown as characters without dots), they have the following differences: display of part to which character is written in each mode background video signal mode external video signal mode internal video signal mode character code note blank data display off data blank data display off data no background displays external video signal displays internal video signal color black-on-white displays background displays external video signal (without background) displays background displays internal video signal color black filling displays background displays external video signal (without background) displays background displays internal video signal color you cannot specify display off data for addresses other than 7e h ( m pd6464a)/fe h ( m pd6465) when using a mask option. blank data, however, can be specified at any address from 00 h to 7d h ( m pd6464a)/fd h ( m pd6465) (address 7f h ( m pd6464a)/ff h ( m pd6465) cannot be used because it contains the end code for second-byte continuous input). the character patterns of the m pd6464acs-001 and gt-101/ m pd6465cs-001 and gt-101 (necs standard models) are shown on the following pages.
m pd6464a,6465 33 6.1 standard character patterns of the m pd6464a note blank data 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 10 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1f 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 28 h 29 h 2a h 2b h 2c h 2d h 2e h 2f h h note h
m pd6464a,6465 34 30 h 31 h 32 h 33 h 34 h 35 h 36 h 37 h 38 h 39 h 3a h 3b h 3c h 3d h 3e h 3f h 40 h 41 h 42 h 43 h 44 h 45 h 46 h 47 h 48 h 49 h 4a h 4b h 4c h 4d h 4e h 4f 50 h 51 h 52 h 53 h 54 h 55 h 56 h 57 h 58 h 59 h 5a h 5b h 5c h 5d h 5e h 5f h h
m pd6464a,6465 35 notes 1. display off data (character address fixed) 2. end code of 2-byte contiguous command (character address fixed) 60 h 61 h 62 h 63 h 64 h 65 h 66 h 67 h 68 h 69 h 6a h 6b h 6c h 6d h 6e h 6f h 70 h 71 h 72 h 73 h 74 h 75 h 76 h 77 h 78 h 79 h 7a h 7b h 7c h 7d h 7e 7f note 2 h note 1 h
m pd6464a,6465 36 6.2 standard character patterns of the m pd6465 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1f h 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 28 h 29 h 2a h 2b h 2c h 2d h 2e h 2f h
m pd6464a,6465 37 30 h 31 h 32 h 33 h 34 h 35 h 36 h 37 h 38 h 39 h 3a h 3b h 3c h 3d h 3e h 3f h 40 h 41 h 42 h 43 h 44 h 45 h 46 h 47 h 48 h 49 h 4a h 4b h 4c h 4d h 4e h 4f h 50 h 51 h 52 h 53 h 54 h 55 h 56 h 57 h 58 h 59 h 5a h 5b h 5c h 5d h 5e h 5f h
m pd6464a,6465 38 note blank data 60 h 61 h 62 h 63 h 64 h 65 h 66 h 67 h 68 h 69 h 6a h 6b h 6c h 6d h 6e h 6f h 70 h 71 h 72 h 73 h 74 h 75 h 76 h 77 h 78 h 79 h 7a h 7b h 7c h 7d h 7e h 7f h 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h 88 h 89 h 8a h 8b h 8c h 8d h 8e h 8f h note
m pd6464a,6465 39 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h 98 h 99 h 9a h 9b h 9c h 9d h 9e h 9f h a0 h a1 h a2 h a3 h a4 h a5 h a6 h a7 h a8 h a9 h aa h ab h ac h ad h ae h af h b0 h b1 h b2 h b3 h b4 h b5 h b6 h b7 h b8 h b9 h ba h bb h bc h bd h be h bf h
m pd6464a,6465 40 c0 h c1 h c2 h c3 h c4 h c5 h c6 h c7 h c8 h c9 h ca h cb h cc h cd h ce h cf h d0 h d1 h d2 h d3 h d4 h d5 h d6 h d7 h d8 h d9 h da h db h dc h dd h de h df h e0 h e1 h e2 h e3 h e4 h e5 h e6 h e7 h e8 h e9 h ea h eb h ec h ed h ee h ef h
m pd6464a,6465 41 notes 1. display off data (character address fixed) 2. end code of 2-byte contiguous command (character address fixed) f0 h f1 h f2 h f3 h f4 h f5 h f6 h f7 h f8 h f9 h fa h fb h fc h fd h fe h ff h note 1 note 2
m pd6464a,6465 42 7. electrical specifications absolute maximum ratings parameter symbol m pd6464acs, 6465cs m pd6464agt, 6465gt unit supply voltage v dd 7v input pin voltage v in C0.3 to v dd +0.3 v output pin voltage v out C0.3 to v dd +0.3 v permissible package power p d 470 320 mw dissipation (t a = 75 c) operating ambient temperature t a C20 to +75 c storage temperature t stg C40 to +125 c output current i o 5ma caution exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. the parameters apply independently. the device should be operated within the limits specified under dc and ac characteristics. recommended operating conditions parameter symbol conditions min. typ. max. unit supply voltage v dd 4.5 5.0 5.5 v operating ambient temperature t a C20 +75 c lc oscillation frequency f osc 478mhz control input high level voltage v cih data, clk, cs, pcl 3.5 v control input low level voltage v cil data, clk, cs, pcl 1.5 v signal output high level voltage v soh i soh =C1ma, v dd =5.0 v 4.5 v signal output low level voltage v sol i sol =1ma, v dd =5.0 v 0.5 v internal signal level setting voltage v vl v cnt 2.5 v dd v external video signal input voltage v i vbsi 0 v dd v current consumption i dd f osc =8mhz 20 ma
m pd6464a,6465 43 ac characteristics (unless otherwise specified, v dd = 5 v, t a = +25 ?c) parameter symbol conditions min. typ. max. unit synchronization signal input t hst 4.0 9.0 m s pulse width pedestal level voltage v ped vbso, internal mode, 1.03 1.29 1.55 v sync-chip level voltage v syt v cnt = 2.5 v, v syt = 1.0 v 0.8 1.0 1.20 v color burst high level voltage 1 v cbh1 1.15 1.44 1.73 v color burst low level voltage 1 v cbl1 0.91 1.14 1.37 v color burst high level voltage 2 v cbh2 1.20 1.50 1.80 v color burst low level voltage 2 v cbl2 0.85 1.07 1.28 v black level voltage v bla 1.03 1.29 1.55 v blue vbs high level voltage v blh 1.26 1.58 1.90 v blue vbs low level voltage v bll 0.88 1.11 1.34 v green vbs high level voltage v grh 1.53 1.92 2.31 v green vbs low level voltage v grl 1.03 1.29 1.55 v white level voltage v whi 1.45 1.82 2.19 v burst phase angle f bsc ntsc, internal mode 170 180 190 deg green phase angle f g 215 225 235 deg blue phase angle f b 350 0 10 deg burst phase angle f bsc1 pal1, internal mode 125 135 145 deg green phase angle f g1 215 225 235 deg blue phase angle f b1 350 0 10 deg burst phase angle f bsc2 pal2, internal mode 215 225 235 deg green phase angle f g2 125 135 145 deg blue phase angle f b2 350 0 10 deg crystal oscillation frequency 1 f xon1 in ntsc mode 14.31818 mhz crystal oscillation frequency 2 f xon2 in pal, secam mode 17.734475 mhz crystal oscillation frequency 3 f xon3 in pal-m mode 14.302446 mhz crystal oscillation frequency 4 f xon4 in pal-n mode 14.328225 mhz character 90% level voltage v90 v cnt = 2.5 v, v syt = 1.0 v 1.53 1.92 2.31 v character 75% level voltage v75 1.45 1.82 2.19 v background 0% level voltage v0 v cnt = 2.5 v, v syt = 1.0 v 1.03 1.29 1.55 v f sc input amplitude f in 300 mv p-p
m pd6464a,6465 44 concept of m pd6464a, 6465 internal video signal level v whi v cbh v grl v bll v grh v blh v bla gnd v cbl v ped v syt
m pd6464a,6465 45 recommended operation timing (t a = C20 to +75 ?c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit setup time t set 200 ns hold time t hold 200 ns minimum clock low-level width t ckl 400 ns minimum clock high-level width t ckh 400 ns clock cycle t tck 1.0 m s cs setup time t css 400 ns cs hold time t csh 400 ns clk slew rate t csr 100 ns data clk cs t set t hold t css t ckl t ckh t tck t csh 90 % 10 % 90 % 90 % 10 % t csr power-on clear specification parameter symbol conditions min. typ. max. unit pcl pin low-level hold period t pcll 10 m s v dd pcl 0 v 0 v 0.9 v dd v dd 0.1 v dd t pcll v dd
m pd6464a,6465 46 8. application circuit diagram (1) 4 multiplier oscillation 1 clk 2 cs 3 data 1 clk cs data v dd osc out osc in pcl gnd fsci fsco xoso xosi vbsi v cnt secam vbso nre test n. c. csyin vsyo hsyo v c + 20 k w v blk 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 10 f + + video-in 2 v p-p 10 f m 5.1 k w 1.2 k w 100 k w 2.2 k w v cc = 5 v 2.2 k w video out 2 v p-p v cc = 5 v 10 h m 100 pf 100 pf csync 20 k w 10 f m 0.01 f m + 30 pf 5 to 30 pf 39 h m m 0.01 f m 300 mv p-p (min) 2200 pf 1.5 k w 5.1 k w 100 kw 1000 pf 4.7 h m 47 pf vd 1 f m ntsc, pal-m: h pal, secam : l 18 pf f sc input <> v dd = 5 v v cc = 5 v cautions 1. the clamp circuit is not necessary when the sync-chip level (1 v dc) can be directly input to pin 24. 2. pin 20 is connected so as to reject unwanted radiation. 3. this application circuit is assumed to input 2v p-p video signals. 4. product equivalent to 1sv163 can be used as a vd (varactor diode).
m pd6464a,6465 47 (2) 4f sc crystal oscillation 1 clk 2 cs 3 data 1 clk cs data v dd osc out osc in pcl gnd fsci fsco xoso xosi vbsi v cnt secam vbso nre test n. c. csyin vsyo hsyo v c v blk 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 10 f + + video-in 2 v p-p 10 f m 5.1 k w 1.2 k w 100 k w 2.2 k w v cc = 5 v 2.2 k w video out 2 v p-p v cc = 5 v 10 h m 100 pf 100 pf csync 10 f m 0.01 f m + 30 pf 5 to 30 pf 39 h m m <> v dd = 5 v v cc = 5 v 5 to 30 pf 4 f sc v dd or gnd open 30 pf cautions 1. the clamp circuit is not necessary when the sync-chip level (1 v dc) can be directly input to pin 24. 2. pin 20 is connected so as to reject unwanted radiation. 3. this application circuit is assumed to input 2v p-p video signals. 4. connect pin 9 to gnd or v dd (do not open). pin 10 should be open.
m pd6464a,6465 48 9. package drawings 24 pin plastic shrink dip (300 mil) s24c-70-300b-2 item millimeters inches b c d f g h j k 1.778 (t.p.) 3.2?.3 0.51 min. 1.78 max. l m 0.17 0.25 7.62 (t.p.) 5.08 max. 6.4?.2 n 0~15 0.50?.10 0.85 min. r 0.070 max. 0.020 0.033 min. 0.126?.012 0.020 min. 0.200 max. 0.300 (t.p.) 0.252?.008 0.010 0.007 0~15 +0.004 ?.003 0.070 (t.p.) +0.10 ?.05 +0.004 ?.005 a 21.95?.2 0.864 +0.009 ?.008 i 3.45?.2 0.136 +0.008 ?.009 notes 1. controlling dimension millimeter. 2. each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. 3. item "k" to center of leads when formed parallel. m b r f h m j i g c d n k 24 13 112 a l
m pd6464a,6465 49 24 pin plastic sop (375 mil) note 1. controlling dimention item millimeters inches e f 2.9 max. 0.125?.075 0.005?.003 0.115 max. b c 1.27 (t.p.) 0.87 max. 0.035 max. 0.050 (t.p.) g 2.50?.2 0.098 detail of lead end b k l p g e f a 15.3 0.602 +0.41 ?.2 +0.017 ?.008 d 0.42 0.017 +0.08 ?.07 h 10.3?.2 0.406 i 7.2?.2 0.283 j 1.6?.2 0.063?.008 k 0.17 0.007 +0.08 ?.07 l 0.8?.2 0.031 m n 0.10 0.12 0.005 0.004 p3 3 +7 ? p24gt-50-375b-2 +7 ? +0.009 ?.008 +0.003 ?.004 +0.009 ?.008 +0.008 ?.009 +0.009 ?.008 +0.003 ?.004 m c m j d 2. each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. millimeter. 24 13 112 s s a n h i
m pd6464a,6465 50 10. recommended soldering conditions solder the m pd6464a, 6465 under the conditions shown below. for the details of the recommended soldering conditions, refer to semiconductor device mounting technology manual (c10535e) . for other soldering methods and conditions, consult nec. surface mount devices m pd6464agt- : 24-pin plastic sop (375 mil) m pd6465gt- : 24-pin plastic sop (375 mil) process conditions symbol infrared ray reflow peak temperature: 235 c or below (package surface temperature), ir35-00-2 reflow time: 30 seconds or less (at 210 c or higher), maximum number of reflow processes: 2 times, vapor phase soldering peak temperature: 215 c or below (package surface temperature), vp15-00-2 reflow time: 40 seconds or less (at 200 c or higher), maximum number of reflow processes: 2 times, wave soldering solder temperature: 260 c or below, flow time: 10 seconds or less, ws60-00-1 maximum number of flow processes: 1 time, pre-heating temperature: 120 c or below (package surface temperature), partial heating method pin temperature: 300 c or below, heat time: 3 seconds or less (per each side of the device). caution apply only one kind of soldering condition to a device, except for partial heating method, or the device will be damaged by heat stress. through-hole devices m pd6464acs- : 24-pin plastic shrink dip (300 mil) m pd6465cs- : 24-pin plastic shrink dip (300 mil) process conditions wave soldering solder temperature: 260 c or below, (only to leads) flow time: 10 seconds or less. partial heating method pin temperature: 300 c or below, heat time: 3 seconds or less (per each lead). caution for through-hole devices, the wave soldering process must be applied only to leads, and make sure that the package body does not get jet soldered.
m pd6464a,6465 51 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
[memo] m pd6464a,6465 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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